BP_V40S_DOT: a single-photon counting pixel readout chip prototype implemented by using the digital-on-top design flow

Purpose The high-energy photon source (HEPS) has set higher-performance requirements for pixel readout chips. The conventional design method, analog-on-top, encounters considerable challenges when implementing pixel readout chips that include high-performance, large-scale, complex digital circuits. Consequently, it is essential to explore a new design method.
Methods This paper proposes a new design method named digital-on-top, which takes digital circuit design as the top level. Based on CMOS 130 nm technology, a pixel readout chip named BP_V40S_DOT has been designed using this method. The chip contains an array of 128 × 96 pixels with a pixel size of 140 μm × 140 μm, working in single-photon counting mode.
Results Using the digital-on-top design method, the BP_V40S_DOT chip achieves serial readout with zero dead time at the system clock with a frequency up to 25 MHz, and the equivalent noise charge is 146 e-. It has implemented a new type of global clock-synchronized digital circuit architecture. Additionally, the new method significantly reduces the design cycle of the pixel readout chip and improves design efficiency.
Conclusion In contrast to the conventional analog-on-top design method, the digital-on-top design method comprehensively accounts for the signal integrity and parasitic effects of the chip, enabling the rapid implementation of ultra-large-scale pixel readout chips with high-performance, complex digital circuits, thus better fulfilling the requirements of HEPS.